One embodiment of the present invention relates to a method for fabricating a doped zone in a semiconductor body, and in one case for fabricating an emitter-forming zone near the surface or for fabricating a buried semiconductor zone.
Diffusion methods in which dopant atoms are indiffused into a semiconductor body and implantation methods are the commonest methods for fabricating a doped semiconductor zone in a semiconductor body or a semiconductor layer. In an implantation method, dopants are implanted into the semiconductor body by irradiating the semiconductor body with highly energetic dopant particles, for example phosphorus ions for fabricating an n-doped semiconductor zone or boron ions for fabricating a p-doped semiconductor zone. In order to activate these implanted dopant ions, that is to say to incorporate them at lattice sites of the crystal lattice of the semiconductor body, and in order to anneal crystal damage resulting from the irradiation, a thermal treatment of the semiconductor body is required after the particle implantation. This thermal treatment required subsequent to an ion implantation is described for example in Sze: “Semiconductor Devices, Physics and Technology”, 2nd edition, ISBN 0-471-33372-7, pages 478 to 480.
Customary temperatures for activating implanted dopant atoms lie in the range of between 800° C. and 1100° C., and are thus so high that the method steps explained for fabricating a doped semiconductor zone have to be effected prior to the fabrication of metallic structures, for example for interconnects, or plastic structures, for example for passivations. The metals and plastics used in the fabrication of semiconductor components would otherwise melt, evaporate or decompose at such high temperatures, as a result of which the component structures fabricated from these materials would be destroyed.
The necessity of being able to fabricate metal structures and plastic structures only after the fabrication of doped semiconductor zones leads to difficulties in the case of components that are produced by means of a so-called thin-wafer technology, as is explained below.
In the case of vertical components, in which the current-carrying path runs in the vertical direction of the semiconductor body, that is to say perpendicularly to a front side and a rear side of the semiconductor body, in order to minimize the on-state and switching losses, it is endeavored to choose the dimensions of the semiconductor body in the vertical direction—that is to say the thickness of said semiconductor body—to be only as large as is necessary with regard to the desired dielectric strength of the component. For power semiconductor components such as, for example, power diodes, power thyristors, power MOSFETS or power IGBTs with a dielectric strength of 600 V, component thicknesses of approximately 60 μm are already sufficient in this case. Since wafers on which a multiplicity of identical components are produced simultaneously and from which the individual chips are sawn out later are difficult to handle with thicknesses of just 60 μm during individual fabrication processes, thicker wafers are usually used as starting material and are thinned by grinding and/or etching toward the end of the fabrication process. In this case, it is desirable, for stability reasons, to carry out as many method steps as possible before the semiconductor body is thinned.
The fabrication of a doped semiconductor zone near the surface, for example of an emitter, on the component side at which the wafer is thinned is in this case possible only after the wafer has been thinned. In this case, the high annealing temperatures required in conventional implantation methods entail the risk of the thinned wafer being damaged for example by the thermomechanical stress under the high thermal loading. What is more, the process steps for fabricating metallic conductor structures and passivation layers can only be carried out on the thinned wafer, which likewise entails the risk of the wafer being damaged or broken.
N-doped semiconductor zones can also be fabricated in a semiconductor body by proton implantation and a subsequent thermal step. This procedure is described for example in Silber et al.: “Improved Dynamic Properties of GTO-Thyristors and Diodes by Proton Implantation”, Technical Digest in International Electron Device Meeting 1985, IEEE, pages 162-165 or in DE 102 43 758 A1. The temperatures for the thermal step, by means of which so-called hydrogen-induced donors are produced, may in this case lie in the range of between 350° C. and 450° C. However, highly doped semiconductor zones such as are required for emitters of power semiconductor components, for example, can scarcely be fabricated by means of such a proton implantation since, according to current knowledge, from the implanted protons only a few percent of the implanted dose lead to the formation of donors.
Moreover, there is a need for a method for fabricating semiconductor zones that are near the surface but buried, in order to improve the so-called “latch-up behavior” of power IGBTs or power MOSFETs. It is known from Baliga: “Power Semiconductor Devices”, PWS publishing, 1995, ISBN 0-534,94098-6, pages 453 to 457, that the latch-up behavior of a power IGBT can be improved by producing, in the p-type body zone of the IGBT, a highly doped, if appropriate flat, semiconductor zone below the n-type emitter of the IGBT.